Bug 2289 - Verilog netlist shorts ports in buses
Verilog netlist shorts ports in buses
Status: CLOSED FIXED
Product: electric
Classification: Unclassified
Component: Tools:Network
1
PC Linux
: P1 blocker
: ---
Assigned To: developers
Depends on:
Blocks:
  Show dependency treegraph
 
Reported: 2011-04-15 06:13 UTC by strubin
Modified: 2011-04-15 20:26 UTC (History)
0 users

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Description strubin 2011-04-15 06:13:47 UTC
** ORIGINALLY POSTED BY Alex Chow on 2009-03-23 13:18:37 **

The verilog netlister appears to be propagating ports to subcells incorrectly, causing different ports of bus to be shorted together.

For example, in:
/import/async/cad/2008/ico_collab08/alex/ColICO/electric/ico_top.delib

Open:
columns:sun{sch}

Write out a verilog netlist. Find line 1677:

tiles__tileSun_lg tile1(.Itune_bot_(Itune[1]), .Itune_top_(Itune[2]), 
      .enTune_bot_(enTune[1]), .enTune_top_(enTune[2]), .recBiasA(recBiasA), 
      .recBiasB(recBiasB), .recBiasC(recBiasC), .recBiasD(recBiasD), 
      .txDin_bot_(txDin[1]), .txDin_top_(txDin[2]), .v2v(v2v), 
      .vBiasLS(vBiasLS), .gnd(gnd), .modN({modN[1], modN[1]}), 
      .tuneMa({tuneMa[1], tuneMa[1]}));

Here (for example), modN[1] is connected to both ports in .modN{}, while the call should really be .modN({modN[1], modN[2]}). This effectively shorts modN[1] to modN[2].
Comment 1 strubin 2011-04-15 16:35:18 UTC
** ORIGINALLY POSTED BY Steven Rubin on 2009-03-23 14:19:15 **

Fixed indexing of signals.
Comment 2 strubin 2011-04-15 16:35:21 UTC
** ORIGINALLY POSTED BY Gilda Garreton on 2009-03-31 11:11:19 **


Released in v8.09g and verified. Closing now.