cyberflex

Networking

No social network accounts found.

cyberflex's Projects

cyberflex's Recent Posts

Topic Project / Forum Last Post in Topic
Mapping boolean equations to library cells, VHDL parser and FPGA technology
Ok, Alliance provides us with something that looks like what we need for approach #3 in VHDL form. This is contents of adder4.vst, which was generated for the same adder4.vhd example (I'm goig to comm . . .
Electric Alliance
  » General
Nadezhin_tiny December 13, 2010 09:13
by: Dmitry Nadezhin
Mapping boolean equations to library cells, VHDL parser and FPGA technology
Due to use "Alliance cells" or use Electric silicone compiler on VHDL containing boolean equations only need to boolean equations on primitive cells. Approach #1: use boolean equations VHDL produc . . .
Electric Alliance
  » General
Nadezhin_tiny December 13, 2010 09:13
by: Dmitry Nadezhin