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Last updated November 28, 2013 10:59, by ChooJun

Multi-objective Evolutionary Algorithm-Based Circuit Optimizer (Cmizer)

The phenomenon of doubling the number of transistors in Integrated Circuits (ICs) every 18 months, and the increase of the required circuit performance in accordance with the Moores law have created immense challenges for the electronic industries [30]. Optimization of circuit parameters is one of the key issues in circuit design, as frequent changes of circuit parameters to optimize the circuit performance and minimize the IC size are necessary to meet the demands and requirements of the global market in faster and smaller electronic products.

This project develops an intelligent Circuit optimizer, i.e., Cmizer, to provide decision support for electronic engineers to design circuits with a faster and easier manner, hence contributing towards the productivity of the electronic industries. Developed under the partnership between Universiti Malaysia Perlis (UniMAP) [40] and Myreka Sdn Bhd (Myreka) [25], and in collaboration with University of Science Malaysia (USM) [41] and Deakin University (Deakin) [10], the Cmizer software tool is targeted to optimize circuit design parameters based on the required circuit performance. It is used in conjunction with any open source circuit simulators, which can produce a netlist, in order to save the cost of circuit design. A Graphical User Interface is designed to allow the users to optimize circuit designs with plug-and-play Multi-Objective Evolutionary Algorithms (MOEAs) in a user-friendly manner. The overall validation results show that Cmizer is capable of saving time and cost required for electronic engineers to tackle circuit design tasks in the electronic industries.

Development Goals of Cmizer

Motivated by the market demand for rapid circuit products, and the competitiveness faced by the Small Medium Enterprises (SMEs) in the electronic industries, this project aims to develop a robust and user-friendly circuit optimizer that is flexible and capable of working in tandem with currently available free circuit simulators. Cmizer enables circuit designers to optimize circuit parameters and ensure the resulting circuit satisfies the design specifications in an easy and semi-automatic manner. This project has received a two-year financial assistance, i.e. Knowledge Transfer Program (KTP) Grant, from the Ministry of Higher Education (MoHE) Malaysia in 2012. Established under the partnership between Universiti Malaysia Perlis (UniMAP) and Myreka Sdn Bhd (Myreka), and in collaboration with University of Science Malaysia (USM) and Deakin University (Deakin), Cmizer is a step forward to assist the local electronic industries in increasing their competitiveness and meeting the challenges in the global market.

The current release of Cmizer , i.e. ver 2.0.x.x, works in tandem with LTSpice [21] (or any other simulators that produce a netlist), which is a free circuit simulation tool in order to reduce the cost needed for purchasing expensive licenses of commercial simulation software packages. Currently, work is in progress to produce the next release of Cmizer, i.e. ver 2.1.x.x, that will support another open source circuit simulator, i.e., NGSpice [12]. Indeed, circuit simulators such as Mentor-Graphic [24], Cadence [3], and Agilent Advanced Design System [39] (ADS) are too expensive for local SMEs. Besides that, not many commercial circuit simulators (let alone free circuit simulators) have built-in optimizers. Among the simulators, ADS is one of the circuit simulation tools that has a number of built-in optimizers, which include Gradient, Random Minimax, Gradient Minimax, Quasi-Newton, Least Path, Minimax, Random Max, Hybrid, Discrete, Genetic, and Simulated Annealing. But, the software cost is high, i.e. estimated about USD 9,000.

Conventionally, circuit parameter optimization is carried out based on the electronic engineers’ experiences, and is often conducted with a trial-and-error manner. The time required for circuit parameter optimization is subject to the complexity of the circuit, the specifications required, the constraints of the circuit parameters, and the number of parameters that need to be optimized. In the business world, time is of essence; therefore, having a circuit optimizer which could help the electronic engineers in optimizing their circuit design in a more convenient and straightforward way with accurate results is vital, especially for inexperienced electronic engineers.

Innovation of Cmizer for Long-term Prospects

The first implementation of MOEA was published in 1985 [7], i.e. Vector Evaluated Genetic Algorithm (VEGA), to solve problems in machine learning [32], [33]. Over the past decade, a number of MOEA have been reported [11], [46], [43], [45], [13], [20], [36]. MOEA have been shown to be useful in generating potential A1 Adenosine receptor antagonists. In this respect, a software tool, i.e. Molecule Commander [42], used MOEA with the concept of Pareto optimality to optimize the dimensionality of the problem. Multi-objective Optimization Problem (MOP) was formed using a pharmacophore model and Support Vector Machine (SVM) models based on molecular fingerprints for subtypes of Adenosine receptor. The niching- based Pareto ranking was used to select the compounds to be used as the classifier inputs, which aimed to select the diverse chemical structures, in each evolution cycle of the experiment. The work [42] reported that the MOEA technique was able to optimize multiple parameters simultaneously, and the solutions appeared feasible and attractive. In short, the MOEA technique allowed an unbiased exploration of the chemical space, and helped medicinal chemists in their drug discovery efforts. In a more recent work [37], an ensemble MOEA optimizer was proposed for feature selection in the multi-objective classification problem. The proposed model was designed by assembling a number of modified Micro Genetic Algorithm (MmGA) [36] as optimizers in an ensemble structure. The ensemble MOEAs modeled in two-fold, i.e., to select a small number of input features for classification and to improve the classification performances of neural network models. The work [37] improved the classification performances of neural network models with a smaller number of input features, i.e. MOP environment, under two benchmark problems and a case study of human motion detection and classification task.

An MOP is concerned with selecting the appropriate values for multiple decision variables with the aims to optimize n (n ≥ 2) objective functions [9] [5]. The MOP differs [8] from the single-objective one because it contains several objectives that require simultaneous optimization. It also has some acceptable performance ranges over all objectives subject to various constraints (also known as the vector of solutions [9]). The MOP aided by the development of evolutionary computational methods, specifically in determining the molecular multi-targets of drug design, has been reported n [17], [18], [22]. In a recent work [2], an adaptive design approach with Pareto-based evolutionary process was introduced to optimize the design of ligands against Polypharmacological profiles or multiple drug targets. The method mimicked the de novo design, which consists of automated learning of medicinal chemistry design tactics for analogues generation, and then tackling them as a MOP. The method was demonstrated by optimizing the Isoindoles towards Polypharmacology objectives with reducing the anti-target activities at each generation of evolutionary strategy. The observation results showed that the method was capable of generating and prioritizing chemical structures equivalent to those devised by medicinal chemists [2].

This invention exploits the advantages of evolutionary computation (a sub-field in Artificial Intelligence) techniques, i.e. MOEAs, for circuit parameter tuning and optimization of circuit performances. A previous work [34] reported that the MOEA was used to undertaking the MOP at the level of Hardware Description Language (HDL). The MOEA-based evolutionary units for Field Programmable Gate Arrays (FPGA) are designed to evolve the required function autonomously with lesser evolution time. The proposed combinational unit consisting of a virtual reconfigurable circuit and MOEA was described in the Very-High-Speed Integrated Circuits (VHSIC) HDL independently of a target platform, i.e. as a soft IP core, and realized in the COMBO6 card. The work reported that a number of circuits were successfully evolved directly in the FPGA, in particular, 3-bit multipliers, adders, multiplexers and parity encoders. In another work [28], combinational circuit, which implemented on a FPGA, was used with a sub population-based MOEA in the environment of Reconfigurable Circuit (RC) architecture. The multiplier circuit was used for testing efficiency of the proposed model in MOP environment. The evolution time of evolving multiplier was reported reducing as compared to incremental evolution and direct evolution system in the experiments [28].

Plug-and-Play of Open Source Circuit Simulator

Cmizer is flexible in which a GUI is developed to allow users to enter all the required parameters, constraints and objectives for optimization purposes. It is downloadable from the web [38]. In order to use Cmizer, the user has to download the free circuit simulator, e.g. LTSpice or NGSpice, from the web. By plugging Cmizer into the circuit simulator, optimization of circuits design with open source circuit simulators is made available. Cmizer capture all the simulation results from the circuit simulator for data analysis and optimization using MOEAs. The best results obtained will be presented via the user interface, in which the appropriate circuit parameter values are suggested, and the expected circuit performance is shown. More MOEA-based optimization techniques will be integrated into Cmizer in the next release so that users can have the flexibility to choose the type of optimization algorithm they intend to use.

Figure 1 shows the overall flow of the Cmizer operation. Cmizer is a Java Swing-based software tool. It starts by reading the circuit design (in netlist format) loaded by the user, and MOEA details from file ”moea.txt”. The input data from the user, i.e. input circuit parameters, constraint limits, specifications, and preference of MOEA optimizer, are captured and written from GUI to file ”cmizer.txt”. These data are reconfigured and submitted to an open source circuit simulator (e.g. LTSpice) to perform circuit simulation. After the first round of simulation, the netlist generated from the circuit simulator is fed to Cmizer for optimization purposes. Cmizer creates a temporary netlist with tuned circuit parameters, and feeds it back to circuit simulator for the second round of simulation. The process continues until the termination criterion (e.g. reaching the maximum number of iteration, or achieving a specific performance measure) is satisfied. Once the optimization process is completed, the best solutions are depicted in the GUI of Cmizer for verification by the user. Since a number of built-in MOEA-based optimizers are incorporated into Cmizer, the user is able to choose any of these available optimizers. If the user is not satisfied with the proposed solutions, changes can be made on the parameters, specifications, and optimizer selection for further optimization cycles.

Figure 1. The overall flow that shows the unique ”Plug-and-Play” features of Cmizer.

Cmizer supports two open source circuit simulators, i.e., LTSpice and NGSpice with three key specifications of circuit design, i.e. Voltage Gain (anom), Cutoff Frequency (fc), and Passband Ripple (arip). User is allowed to plug-and-play his/her preference circuit simulator into Cmizer by modifying the Regular Expression (RE) of Java in handling these three key specifications, which located in the method evaluate of Example illustration based on LTSpice log as follows.

  1. Sample line for anom:
    • anom: mag(v(out))=(-2.18515e-005dB,0°) at 10
    • Cmizer operates it as minimization manner, and the captured value is (10 ^ (-2.18515e-005/20)) x -1 = -0.9999974842562566. Say our aims is to maximize the Gain, i.e. ideal values fall between 0.9 to 1.0, and Cmizer yield a very good result for it, i.e. 0.9999974842562566.
  2. Sample line for fc:
    • fc: frequency=(59.9662dB,0°) at 996.12
    • Cmizer operates it as minimization manner, and the captured value is 996.12 x -1 = -996.12. Say our aims is to maximize the Cutoff, i.e. ideal values fall between 980 to 1000, and Cmizer yield a very good result for it, i.e. 996.12.
  3. Sample line for arip:
    • arip: amax/amin=(3.01271dB,0°)
    • Cmizer operates it as minimization manner, and the captured value is 3.01271
 The RE for LTSpice:
 Voltage Gain: ^anom: mag\\(v\\(out\\)\\)=\\({1}(.*?),(.*?)\\) at{1} (.*?)$
 Cutoff Frequency: ^fc: frequency=\\({1}(.*?),(.*?)\\) at{1} (.*?)$
 Passban Ripple: ^arip: amax/amin=\\({1}(.*?),(.*?)\\){1}$
 The RE for NGSpice:
 Voltage Gain: ^\\s*anom\\s*=\\s*(.*?)\\s*$
 Cutoff Frequency: ^\\s*fc\\s*=\\s*(.*?)\\s*$
 Passband Ripple: ^\\s*arip\\s*=\\s*(.*?)\\s*$

Plug-and-Play of MOEA-based Optimizer

At present, Cmizer contains a total of five sample MOEAs. In addition, the user is allowed to plug-and-play his/her own developed or preference open source MOEA into Cmizer. In this case, the user first needs to locate his/her own algorithm, e.g. ”doMyMmGA”, in Java method, as in ””. The next step is to invoke the new created Java method (e.g. ”doMyMmGA”) within the line of existing Java method named ”runIt” in ””. The user needs to provide a name for each new MOEA technique, e.g. ”MyMmGA”, in the array of variable ”moea” inside ””. Then, re-run Cmizer after compiling all the Java source codes, and the name of the new MOEA technique will appear as in the item 4 shown in Figure 2. The details for integrating the user own MOEA technique into Cmizer can be found in the Class Diagram. The Cmizer Class Diagram is implemented with the generic Java inheritance concepts that allow more research and development efforts to be incorporated in future.

 public Algorithm doMyMmGA(Properties optiSetting, 
 	double[] loLimit, double[] upLimit, String[] uom) 
 	throws JMException, IOException 
   Problem problem = null; 
   Object[] solType = 
     { "Real", loLimit.length, loLimit, upLimit, uom }; 
   Algorithm algorithm = new MyMmGA("myCircuitProblem"); 
   algorithm.setInputParameter("populationSize", 200); 
   Crossover crossover = CrossoverFactory.getCrossoverOperator("probability", 0.8); 
   algorithm.addOperator("crossover", crossover); 
   Mutation mutation = MutationFactory.getMutationOperator("probability", 0.8); 
   algorithm.addOperator("mutation", mutation); 
   Selection selection = (Selection) 
  	SelectionFactory.getSelectionOperator("BinaryTournament", null); 
   algorithm.addOperator("selection", selection); 
   return algorithm; 

Instead of tuning the circuit parameter manually or buying an expensive circuit simulation software with built-in optimizers, Cmizer helps save time and cost by using state-of-the-art MOEA optimization techniques that can be linked with open-source circuit simulators available from the web. The plug-in feature of Cmizer is convenient for the user to test and optimize the designed circuits as well as his/her own MOEA technique. By combining with the open-source circuit simulators, the cost needed for circuit parameter optimization is significantly reduced, and electronic engineers can complete their circuit designs in a faster pace, in order to meet the demands of the electronic industry.

Demo with Circuit Design

Video clips are best view with VLC Player

  • Cmizer The demo of prototype release.
  • Cmizer This demo was conducted with tunned MOEA's parameters in Ubuntu and NGSpice. The optimized results of NSGAII were obtained after end of 2 minutes.

  • Cmizer This demo shows the optimization task with built-in MOEA, i.e. NSGAII, and posblpfsk filter. The experiment was conducted with not tunned MOEA's parameters in Windows XP and LTSpice.

  • Cmizer This demo shows the optimization task with built-in MOEA, i.e. NSGAII, and posblpfsk filter. The experiment was conducted with tunned MOEA's parameters in UBuntu and NGSpice. The optimized results of NSGAII were obtained after end of 1 minute.

  • Cmizer This demo shows the optimization task with built-in MOEA, i.e. NSGAII, and all bundled circuit designs (6 sets). The experiment was conducted with non-tunned MOEA's parameters in Fedora and NGSpice.

Case Study with Published MOEA

Video clip is best view with VLC Player

  • Cmizer 2.x.x.x Case Study: This case study shows the integration of Cmizer and a published MOEA, i.e. MmGA [36], with NGSpice using the posblpfsk filter, which has 10 input variables. Three objectives, i.e. voltage gain (the higher the better), cutoff frequency (the higher the better), and ripple band (the lower the better), are required in circuit design. The experiment was conducted in Ubuntu and NGSpice, and two sets of optimized results were obtained after end of 4 minutes.

Marketability and Plans of Cmizer

With the flexibility of the GUI of Cmizer, the user is allowed to modify the parameters, constraints and objective of the circuit design. This tool is capable of assisting electronic engineers in SMEs as well as educational and research institutions in circuit design tasks. In business, Cmizer contributes significantly towards time and cost savings in complex circuit design tasks. In academic institutions, it can be used to promote education and research on circuit design.

To validate the effectiveness of Cmizer, a real-world evaluation study had been conducted. A total of 3 practicing engineers from an SME involved in circuit design were invited to design a circuit that should meet certain specifications (e.g. gain and phase margins) based on their experience without assistance of any circuit optimization tools. During the 3-hour evaluation session, the engineers were given a circuit design in LTspice (that comes with no built-in optimizers), and were asked to tune the circuit parameters based on their experience, or knowledge from books. Two engineers spent more than 2 hours to meet the circuit specifications, while one engineer was not able to do so within the maximum 3-hour time frame. As compared with the use of Cmizer, the required specifications were able to be fulfilled within 15-20 minutes. As a result, it is evidenced that Cmizer contributes significantly towards saving of engineering time in circuit design tasks, which is equivalent to the value of profit return to the company.

In terms of the marketability plan, we encourage researchers and practitioners from all over the world to contribute newly developed optimization algorithms into Cmizer so that it becomes more flexible, practical, and robust from time to time. All contributed personnels can be provided with loyalty through the amount of charges gained from the number of downloads in the web. In the real world, there are a lot of engineering problems which involve parameter optimizations such as chemical process, instrumental design, manufacturing planning, etc. As the MOEA optimization techniques are generic in nature (and not just tailored to circuit parameter optimization), Cmizer can be further developed to work with other types of engineering problems that required optimization so as to extend the usability and marketability of Cmizer.

Besides LTSpice/NGSpice, we are currently developing the software for plug-and-play features in other free simulators. The aim is to increase the robustness of the MOEA optimization techniques from time to time so as to increase the flexibility to meet the requirements of various applications. As an example, a case study on chemical process optimization has been conducted and exhibited in the Invention and New Product Exposition (INPEX 2012) at Pittsburgh, USA as well as in the Cyber International Genius Inventor Fair (CIGIF 2012) at South Korea.

System Configuration of Cmizer

Cmizer is developed using the Java programming language. The developed application can be executed on multiple operating systems without the need to re-compile the source codes. We have tested Cmizer with a personal computer with 2Gb RAM and 50Mb hard drive space in three types of operating systems, as follows.

  1. Ubuntu 11.04, 12.04 [4]
  2. Fedora 19 [31]
  3. Microsoft Windows XP, 7

Open Source of Cmizer

Cmizer uses at least eight open source technologies for its development, as follows.

  1. Apache Log4J [1]
  2. Apache Commons Math [14]
  3. Jahmm [16]
  4. Jsci [23]
  5. jMetal [26]
  6. OpenCSV [15]
  7. LTSpice [21]
  8. NGSpice [12]
  9. Java Swing [27]

Cmizer is devised based on the Java Swing development framework. It uses Apache Log4J as part of the GUI, especially for debugging and audit trail logging. Besides that, Apache Commons Math, Jahmm, and Jsci are the core framework used for the development of the MOEA techniques. Five MOEA techniques from jMetal, an open source MOEA library, are adopted in Cmizer. Both LTSpice and NGSpice are the open source circuit simulators which Cmizer uses for circuit design optimization. OpenCSV is used as the median of interoperability within between MOEA and circuit simulators via the specification of the Comma-Separated Values (CSV) file format. Cmizer utilizes open source middlewares; thus involving no cost of software licensing. Cmizer is a sustainable platform for solving real-world circuit design optimization problems, and it allows users to adopt built-in MOEA techniques for multi- objective optimization of circuit parameters efficiently and effectively.

Graphical User interface (GUI) of Cmizer

The logical flow of Cmizer application is as follows. A GUI is designed to allow user submit a circuit design job for optimization. The installed circuit simulator, i.e. LTSpice or NGSpice, with pre-loaded MOEA optimizers are used to produce the circuit optimized results.

The GUI of Cmizer version 2.1.x.x requires a minimum screen resolution of 1024x800 in order to have a proper display. The function of ”maximizing” in Cmizer has been tested with a screen resolution of 1920x1080. Cmizer is packaged in a zip file with the version number for ease of binary distribution. Java and circuit simulator (i.e., LTSpice) packages need to be installed separately by the user. As shown in Figure 2, various tasks can be performed, viz.,

  1. Capturing the lower and upper limit values for each variable and automatically generating the values according to the
  2. Circuit netlist file,
  3. Displaying the computed ideal solution / maximum performance of the circuit
  4. Displaying the suggested final solutions after the computational process
  5. Capturing the type of optimizer engines available in Cmizer
  6. Linking the help module for Cmizer
  7. Linking the back-end engine of Cmizer

Figure 2. The new interface for Cmizer version 2.x.x.x

The user is allowed to configure Cmizer and its associated MOEA techniques via the GUI (as shown in item 7, Figure 2). The MOEA settings and the ranges of the input variables are auto-saved, if any changes are found, in the sub-directory named log/. The MOEA settings can be configured by clicking the ”Setting” button (next to the ”Run Now” button), and altering the given values for various parameters. All updated settings are saved in ”cmizer.txt” and ”moea.txt”. To port the same settings to another copy of Cmizer, the user just needs to copy these two files from directory ”data/circuit/” and overwrite them in Cmizer installed in other computers.

The ranges of the input variables are editable using the GUI (as shown in item 1, Figure 2), which simplifies the task of configuration. The input variables in the GUI is auto-retrieved, based on the given content of the netlist file in the sub-directory ”data/circuit/”. However, the netlist filename and parameter names need to follow a specific naming convention in Cmizer.

The objective function in Cmizer receives a range of values, or a single value (i.e. with the same value for the lower and upper limits) during the optimization process (as shown in item 2, Figure 2). The name of the objectives in Cmizer is dynamically loaded based on the given netlist file in ”data/circuit/”.

The computed results, including the intermediate and final optimized results, are captured in the TextArea panel at the bottom part of the Cmizer GUI (as shown in item 3, Figure 2). It is designed to ease the ”copy and paste” function with the scrolling activity by the user. There are 6 tested sample circuit designs, i.e. the Spice-based netlist files, bundled together with Cmizer.

Future Roadmap of Cmizer

A service-based platform is proposed in next version with the details at here

Sample Circuits

Filter circuits are used in a wide variety of applications. In the field of telecommunication, data acquisition systems usually require anti-aliasing low-pass filters as well as low-pass noise filters in their preceding signal conditioning stages. A low-pass filter is an electronic filter that passes low-frequency signals and attenuates (reduces the amplitude of) signals with frequencies higher than the cutoff frequency. In the lower frequency range (1 Hz to 1 MHz), however, the inductor value becomes very large and the inductor itself gets quite bulky, making economical production difficult. In other cases, the high pass filter is used to block dc offset in high gain amplifiers or single supply circuits. In summary, filters can be used to separate signals, passing those of interest, attenuating the unwanted frequencies.

An active filter is a type of analog electronic filter that uses active components such as an amplifier. Amplifiers included in a filter design can be used to improve the performance and predictability of a filter, while avoiding the need for inductors (which are typically expensive compared to other components). Often the filters operate at unity gain to lessen the stringent demands on the opamp’s open-loop gain. When operating at unity gain, the non-inverting amplifier reduces to a voltage follower, thus inherently providing superior gain accuracy. There are two topologies for a second-order low-pass filter, the Sallen-Key and the Multiple Feedback (MFB) topology. The general Sallen-Key topology allows for separate gain setting. However, the unity-gain topology is usually applied in filter designs with high gain accuracy, unity gain, and low quality factor (Q < 3). On the other hand, MFB topologies are commonly used in filters that have high Q and require a high gain.

Fifth-Order Sallen key High-Pass Filter

Fifth-Order Negative Unity Gain Multiple Feedback Butterworth Low Pass Filter

Fifth-Order Negative Unity Gain Sallen-Key Butterworth Low Pass Filter

Fifth-Order Positive Unity Gain Multiple Feedback Butterworth Low Pass Filter

Fifth-Order Positive Unity Gain Sallen-Key Butterworth Low Pass Filter

Third-Order Sallen Key High-Pass Filter

Multi-objective Evolutionary Algorithm (MOEA) of Cmizer

There are a total of five MOEA available in Cmizer, i.e., Non-dominated Sorting Genetic Algorithm-II (NSGAII), Strength Pareto Evolutionary Algorithm 2 (SPEA2), Indicator-based Evolutionary Algorithm (IBEA), Fast Pareto Genetic Algorithm (FastPGA), and Pareto Archived Evolution Strategy (PAES). The details of the MOEA techniques are as follows.

  • NSGAII: The NSGAII [11] technique is an improved version of the Non-dominated Sorting Genetic Algorithm (NSGA) [35]. It uses the crowding distance (CD) to estimate the density of solutions surrounding a particular solution in the population by computing the average distance of two points on either side. It uses the crowded comparison operator to determine the chosen solution where non-dominated solutions are preferred over dominated solution as well as the one that resides in the less crowded region is preferred among non-dominated solutions. It also implements the elitism strategy to combine the best parents with the best offspring. The CD measure is used in other MOEA techniques, such as the Micro Genetic Algorithm (mGA) [9], modified mGA [36], the niching-based differential-evolution algorithm [29], and the preference-based solution selection algorithm [19]. The flow of NSGAII shows as follow.


  • SPEA2: The SPEA2 [46], [43] technique is an improved version of Strength Pareto Evolutionary Algorithm (SPEA) [44] in three aspects: (i) more fine-grained fitness assignment for individual domination; (ii) guided search of the nearest neighbour density estimation; (iii) enhanced archive pruning to preserve the boundary of the pareto optimal set. The algorithm of SPEA2 shows as follow.


  • IBEA: The IBEA uses a binary indicator, i.e. Hypervolume, to eliminate dominance ranking to undertaking the multi- objective search problems [45]. The algorithm of IBEA shows as follow.


  • FastPGA: The FastPGA is a real-coded multi-objective genetic algorithm with a fitness assignment and ranking strategy [13]. The elitism operator is used to achieve the fast propagation of the Pareto optimal solution set. The algorithm of FastPGA shows as follow.


  • PAES: The PAES is designed with two aims: 1) multi-objective search that confines to local search with a small change in mutation operator,2) multi-objective search that moves from a current location to a nearby neighbour [20]. An archive is used to keep the previously found non-dominated solutions when comparing pairs of solution in the search activity. PAES treats all non-dominated solutions as having the same value, and it uses an archive as a means for estimating the true dominance ranking of a pair of solutions. The flow of PAES shows as follow.


Quick Start Guide for Cmizer


Please install the following software before start using the Cmizer (2.x.x.x):

  1. LTSpice, and/or NGSpice,
  2. Java Runtime Engine (JRE) or Java Development Kit (JDK) version 1.6,
  3. Note that, video clips below are best view with VLC Player

Binary from Cmizer's web site

  1. Uncompress the downloaded file
  2. Run Cmizer with the file as follows
    • For Linux: Issue command ./run_[circuit_design].sh after change directory to particular [circuit_design], see demo
    • For Windows: Double-clicks the run_[circuit_design].bat file at particular [circuit_design], see demo
  3. Examine the range of input variables and objectives
  4. Examine the Circuit Simulator path, e.g., LTSpice installed at C:\Program Files\LTC\LTspiceIV\ in Windows XP, or NGSpice installed at /usr/bin/ or /usr/local/bin/
  5. Configure the Cmizer, especially the MOEA setting, before click on the "Run Now" button at Cmizer's GUI.

Checkout Source Code from SVN

  1. Check out the source code using SVN client
  2. Compile the source code using Java
  3. Execute the Cmizer using the
  4. Watch demo using Eclipse with Subclipse which applicable to Linux and Windows

Naming Convention for Netlist

For version 2.x.x.x

  1. The input variables in Netlist file need to follow the naming convention of r[x]opt, where the [x] is the sequence number of your circuit component. Please look at the sample Netlist files in directory of data/circuit/.
  2. Cmizer supports multi-objective minimization for Voltage Gain, Cutoff Frequency, and Passband Ripple. These objectives need to be declared using variable name of anom, fc, and arip, respectively.


  1. Naming convention for version: [Major_changes].[Simulator_supported].[Feature_enhancement].[Bugs_fixed]
    • Simulator_supported:
      • 0=LTSpice for Windows, e.g. x.0.x.x
      • 1=NGSpice for Linux and Windows, e.g. x.1.x.x
  2. Cmizer bugs reporting at
  3. The latest (in progress) development source code is available at SVN, or checkout it using the given information at destination page.
  4. Obtain the tested binary, source code and each release details at here.


The software distribution is based on GNU General Public License, version 3 (GPL-3.0), see more details at URL

Cmizer Video Clip

Refer to Section here

Cmizer Screen Capture

Version 2.x.x.x

The Graphical User Interface (GUI) of Cmizer version 1.x.x.x is updated (as in below Figure). The use of WindowBuilder is out-dated for the development of Cmizer version 2.x.x.x. The new GUI, i.e. version 2.x.x.x, is faster in the application launching speed as compared with that in version 1.x.x.x.

Version (prototype release)

  1. In Cmizer, the specifications achieved per evolutionary iteration of the optimization are depicted in the interface of output performance. The user can observe the proximity of the result towards the required specifications from time to time.
  2. The gain value in LTSpice screen based on Cmizer's pareto optimal set
  3. The ripple value in LTSpice screen based on Cmizer's pareto optimal set
  4. The phase value in LTSpice screen based on Cmizer's pareto optimal set
  5. The cutoff value in LTSpice screen based on Cmizer's pareto optimal set

Personnel and Work Assignment of Cmizer

There are five members in our Cmizer team as follows.

  1. Mr. Choo Jun TAN, the team lead: student of USM;
  2. Mr. Wei Jer LIM, the team member: student of UniMAP;
  3. Mr. Kian Meng TEY, the industry mentor: circuit design expert of Myreka;
  4. Dr. Siew Chin NEOH, the academic mentor: lecturer of UniMAP; and
  5. Professor Dr. Chee Peng LIM, the academic mentor: lecturer of USM/Deakin.

Mr Lim, Dr Neoh, Mr Tan, Mr Tey, and Professor Lim (from left to right)

Professor Lim and Dr Neoh are the coordinator cum mentor between academic and industrial organisations. Both of them also act as researchers in contributing state-of-the-art knowledge pertaining to MOEA techniques in this project. Mr Tey is the contributor industrial partner for the development of Cmizer. Together with Myreka staff, he provides useful technical and knowledge support from industrial perspective for the development of Cmizer.

The main development tasks of Cmizer are carried out by Mr Tan and Mr Lim. Mr Tan resumes the key role as the technical developer and system analyst for the Software Development Life Cycle (SDLC). Circuit design optimization is one of his current research interests, especially in MOEA techniques and their application to undertaking real-world MOPs. Mr Lim contributes towards the development tasks of SDLC for various operating systems using Java programming language for circuit design and analysis tasks using circuit simulators.


  1. Bronze Medal for CIGIF 2012 - The 3rd Cyber International Genius Inventor Fair 2012 in South Korea


MOEA related papers by the Cmizer team are as follows:

  1. C. J. Tan, C. P. Lim, and Y.-N. Cheah, A modified micro genetic algorithm for undertaking multi-objective optimization problems, Journal of Intelligent and Fuzzy Systems, vol. 24, no. 3, pp. 483 495, 2013.
  2. C. J. Tan, C. P. Lim, Y.-N. Cheah, and S. C. Tan. (2013). Classification and Optimization of Product Review Information Using Soft Computing Models. Proceedings of 1st International Symposium on Affective Engineering (ISAE) (2013) pp 115-120, Japan Society of Kansei Engineering, Japan.
  3. C. J. Tan, C. P. Lim, and Y.-N. Cheah, A multi-objective evolutionary algorithm-based ensemble optimizer for feature selection and classification with neural network models, Neurocomputing, Volume 125, Pages 217-228, 11 February 2014.

Circuit analysis related papers by the Cmizer team are as follows:

  1. Chong W. K. and Neoh S. C. (2012). Improved Particle Swarm Optimization (PSO) for Performance Optimization of Electronic Filter Circuit Design. Applied Mechanics and Materials: Mechanical and Electrical Technology IV, Vols. 229-231 (2012) pp 1643-1650, Trans Tech Publications, Switzerland.
  2. Lim, W.J., Gerald, L.J.X., Neoh, S.C., and Marzuki, A. (2012), GA-based Optimization for Circuit Design Assistance. The 3rd International Conference of Intelligent Systems, Modelling, and Simulation, 8-10 February 2012, Sabah.
  3. Lau, T. L., Neoh S. C., Marzuki, A. (2012), An Optimization of 15.12 GHz SPDT Switch Using Particle Swarm Optimization Algorithm. The 4th International Conference on Intelligent and Advanced Systems, 12th -14th June 2012, Kuala Lumpur.
  4. Chong W. K. and Neoh S. C. (2012), Improved Particle Swarm Optimization (PSO) for Performance Optimization of Electronic Filter Circuit Design. International Conference on Nanomaterials and Electronics Engineering, 24th -26th July 2012, Kuala Lumpur.
  5. Cheng K. L. and Neoh S. C. (2012), 4th Order Sallen Key High Pass Filter Optimization using Genetic Algorithm. The 4th Asia Symposium on Quality Electronic Design (ASQED 2012), 9th -11th July 2012, Penang, Malaysia.
  6. Ng, P. F., Neoh S. C., and Nor. R. Y. (2012), 2nd Order Multiple Feedback Fully Differential Low Pass Filter Optimization Based on Particle Swarm Optimization (PSO) Method and Design of Experiment (DOE) Approach, International Conference on Computer Engineering & Mathematical Sciences 2012 (ICCEMS 2012).
  7. Cheh, C. M., Neoh S. C., and Nor. R. Y. (2012), Fifth Order Active Low Pass Filter Optimization Based on Genetic Algorithm with Triple Populations, International Conference on Computer Engineering & Mathematical Sciences 2012 (ICCEMS 2012).
  8. Tai, K. H. and Neoh S. C. (2012), Genetic Algorithm Optimization For 4th -Order Multiple Feedback High Pass Filter, International Conference on Computer Engineering & Mathematical Sciences 2012 (ICCEMS 2012).
  9. Eng, K.K., Neoh, S.C. (2012). Genetic Algorithm Optimization For 4th Order Multiple Feedback High Pass Filter, IEEE International Conference on Circuits & Systems (ICCAS2012), 3-5th October, Kuala Lumpur, Malaysia.


If you would like to cite Cmizer, cite the following info:

Choo Jun Tan and Wei Jer Lim and Siew Chin Neoh, Chee Peng Lim and Kian Meng Tey, Cmizer: Multi-objective Evolutionary Algorithm-Based Circuit Optimizer, 2013, software available at

The bibtex format is as follows

@Manual{cmizer2013, author = {Choo Jun Tan and Wei Jer Lim and Siew Chin Neoh and Chee Peng Lim and Kian Meng Tey}, title = {{Cmizer}: Multi-objective Evolutionary Algorithm-Based Circuit Optimizer}, year = {2013}, note = {Software available at \url{}} }


See the details at here


See the details at here

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