cyberflex

Posted: November 19, 2010 11:29 by cyberflex

Due to use "Alliance cells" or use Electric silicone compiler on VHDL containing boolean equations only need to boolean equations on primitive cells. Approach #1: use boolean equations VHDL produced by Alliance. For this purpose needs to make Electric VHDL parser understand constructions likes "a <= b OR (c AND d)". Also needs algorithm of mapping these ANDs and ORs to primitive cells of the cell library used. This is likely almost the same algorithm as mapping logic to FPGA cells... So the question is: what is the current state of FPGA map process in Electric and how it si organized internally? Approach #2: Looke for the method to save Allaince to created "fully schematic" VHDL (where boolean equations are already converted to and_35u(c,d,wire0009); or_35u(wire0009,b,a); ...) Approach #3 : use Alliance netlist files in Electric silicone compiler, the problem is that netlist formats of both programs seem to be quite different Example VHDL file: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_arith.ALL; use IEEE.STD_LOGIC_unsigned.ALL; entity Adder4 is port ( A : in Std_Logic_Vector(3 downto 0) ; B : in Std_Logic_Vector(3 downto 0) ; C : out std_logic; RESULT : out Std_Logic_Vector(3 downto 0) ); end Adder4; architecture DataFlow OF Adder4 is begin RESULT <= std_logic_vector( unsigned(A) + unsigned(B) ); end DataFlow; Here is example of Allaince VASY tool output:   Generated by VASY  ENTITY adder4 IS PORT( a : IN BIT_VECTOR(3 DOWNTO 0); b : IN BIT_VECTOR(3 DOWNTO 0); c : OUT BIT; result : OUT BIT_VECTOR(3 DOWNTO 0); vdd : IN BIT; vss : IN BIT ); END adder4; ARCHITECTURE VBE OF adder4 IS SIGNAL rtlsum_0 : BIT_VECTOR(3 DOWNTO 0); SIGNAL rtlcarry_0 : BIT_VECTOR(3 DOWNTO 0); BEGIN c <= '0'; rtlcarry_0(0) <= '0'; rtlsum_0 <= ((a XOR b) XOR rtlcarry_0); rtlcarry_0(3 downto 1) <= (((a(2 downto 0) AND b(2 downto 0)) OR (a(2 downto 0) AND rtlcarry_0(2 downto 0) )) OR (b(2 downto 0) AND rtlcarry_0(2 downto 0))); result <= rtlsum_0; END VBE; If approach #1 is taken, then Electric VHDL parser (CompileVHDL.java) may be extended to support some more tokens described in VHDL BNF. Maye be it would be reasonable use JavaCC or Antlr parser generators to simplify support of standard grammar descriptor files ... May be Electric FPGA technology could be used for for mapping of VASY output results ? 