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Mapping boolean equations to library cells, VHDL parser and FPGA technology

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Replies: 3 - Last Post: December 13, 2010 09:13
by: Dmitry Nadezhin
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Posted: November 19, 2010 11:29 by cyberflex
Due to use "Alliance cells" or use Electric silicone compiler on VHDL containing boolean equations only need to boolean equations on primitive cells.




Approach #1: use boolean equations VHDL produced by Alliance.
For this purpose needs to make Electric VHDL parser understand
constructions likes "a <= b OR (c AND d)". Also needs algorithm of mapping these AND-s
and OR-s to primitive cells of the cell library used.
This is likely almost the same algorithm as mapping logic to FPGA cells...
So the question is: what is the current state of FPGA map process in Electric and how it si organized internally?

Approach #2:
Looke for the method to save Allaince to created "fully schematic" VHDL (where boolean equations are already converted to and_35u(c,d,wire0009); or_35u(wire0009,b,a); ...)

Approach #3 : use Alliance netlist files in Electric silicone compiler,
the problem is that netlist formats of both programs seem to be quite different



Example VHDL file:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_arith.ALL;
use IEEE.STD_LOGIC_unsigned.ALL;


entity Adder4 is

port ( A : in Std_Logic_Vector(3 downto 0) ;
B : in Std_Logic_Vector(3 downto 0) ;
C : out std_logic;
RESULT : out Std_Logic_Vector(3 downto 0) );

end Adder4;


architecture DataFlow OF Adder4 is
begin

RESULT <= std_logic_vector( unsigned(A) + unsigned(B) );

end DataFlow;



Here is example of Allaince VASY tool output:

-
-- Generated by VASY
--
ENTITY adder4 IS
PORT(
a : IN BIT_VECTOR(3 DOWNTO 0);
b : IN BIT_VECTOR(3 DOWNTO 0);
c : OUT BIT;
result : OUT BIT_VECTOR(3 DOWNTO 0);
vdd : IN BIT;
vss : IN BIT
);
END adder4;

ARCHITECTURE VBE OF adder4 IS

SIGNAL rtlsum_0 : BIT_VECTOR(3 DOWNTO 0);
SIGNAL rtlcarry_0 : BIT_VECTOR(3 DOWNTO 0);

BEGIN

c <= '0';
rtlcarry_0(0) <= '0';
rtlsum_0 <= ((a XOR b) XOR rtlcarry_0);
rtlcarry_0(3 downto 1) <= (((a(2 downto 0) AND b(2 downto 0)) OR (a(2 downto 0) AND rtlcarry_0(2 downto 0)
)) OR (b(2 downto 0) AND rtlcarry_0(2 downto 0)));
result <= rtlsum_0;
END VBE;





If approach #1 is taken, then Electric VHDL parser (CompileVHDL.java) may be extended to support some more tokens described in
VHDL BNF. Maye be it would be reasonable use JavaCC or Antlr parser generators to simplify support of standard grammar descriptor files ...
May be Electric FPGA technology could be used for for mapping of VASY output results ?




Posted: November 26, 2010 19:28 by Dmitry Nadezhin
Here are the links about FPGA technology in Electric:


The structure of FPGA is defined by text file with hierarchical description .
Leafs of the description are represented by Electric PrimitiveNodes.
Higher levels are represented by Electric Cells.
The structure contains programming points (pips and repeaters) with hierarchical path names. They can be activated/deactivated by Electric Variable on the top Cell. The value of the Variable is a list of paths of active points.

When Electric visualizes FPGA structure it shows active points and it can hide unused FPGA wires. Electric GUI can help to edit the Electric Variable with a list of active points graphically.

Unfortunately this code is commented now, It worked in Electric 8.07or before .

Electric can save/restore programmed FPGA in/from Jelib file.

The FPGA technology is only for visualization now. Electric doen;t know logic equations of FPGA primitives. There are no tools to calculate parasitics/delays, to write a bitstream or to convert to real layout.

If we want to map VHDL design into a list of active programming point in Electric FPGA technology, than we need to repair FPGA technology and to define some fake FPGA structure.

If we want to map VHDL design into a gate library
then my preference is Approach #2 or Approach #3 .


Posted: December 06, 2010 12:23 by cyberflex
Ok,
Alliance provides us with something that looks like what we need for approach #3 in VHDL form.

This is contents of adder4.vst, which was generated for the same adder4.vhd example (I'm goig
to commit this example in svn):

entity adder4 is
port (
a : in bit_vector(3 downto 0);
b : in bit_vector(3 downto 0);
result : out bit_vector(3 downto 0);
vdd : in bit;
vss : in bit
);
end adder4;

architecture structural of adder4 is
Component inv_x4
port (
i : in bit;
nq : out bit;
vdd : in bit;
vss : in bit
);
end component;

Component a2_x2
port (
i0 : in bit;
i1 : in bit;
q : out bit;
vdd : in bit;
vss : in bit
);
end component;

Component inv_x2
port (
i : in bit;
nq : out bit;
vdd : in bit;
vss : in bit
);
end component;

Component nao2o22_x1
port (
i0 : in bit;
i1 : in bit;
i2 : in bit;
i3 : in bit;
nq : out bit;
vdd : in bit;
vss : in bit
);
end component;

Component xr2_x1
port (
i0 : in bit;
i1 : in bit;
q : out bit;
vdd : in bit;
vss : in bit
);
end component;

Component buf_x2
port (
i : in bit;
q : out bit;
vdd : in bit;
vss : in bit
);
end component;

signal not_a : bit_vector( 1 downto 1);
signal not_b : bit_vector( 2 downto 2);
signal xr2_x1_sig : bit;
signal xr2_x1_3_sig : bit;
signal xr2_x1_2_sig : bit;
signal rtlcarry_0_2 : bit;
signal rtlcarry_0_1 : bit;
signal not_rtlcarry_0_2 : bit;
signal not_rtlcarry_0_1 : bit;
signal nao2o22_x1_sig : bit;
signal mbk_buf_rtlcarry_0_2 : bit;
signal mbk_buf_rtlcarry_0_1 : bit;
signal inv_x2_sig : bit;
signal inv_x2_2_sig : bit;
signal a2_x2_sig : bit;
signal a2_x2_2_sig : bit;

begin

not_rtlcarry_0_2_ins : inv_x2
port map (
i => rtlcarry_0_2,
nq => not_rtlcarry_0_2,
vdd => vdd,
vss => vss
);

not_rtlcarry_0_1_ins : inv_x4
port map (
i => rtlcarry_0_1,
nq => not_rtlcarry_0_1,
vdd => vdd,
vss => vss
);

not_a_1_ins : inv_x2
port map (
i => a(1),
nq => not_a(1),
vdd => vdd,
vss => vss
);

not_b_2_ins : inv_x2
port map (
i => b(2),
nq => not_b(2),
vdd => vdd,
vss => vss
);

rtlcarry_0_1_ins : a2_x2
port map (
i0 => b(0),
i1 => a(0),
q => rtlcarry_0_1,
vdd => vdd,
vss => vss
);

a2_x2_ins : a2_x2
port map (
i0 => not_a(1),
i1 => not_rtlcarry_0_1,
q => a2_x2_sig,
vdd => vdd,
vss => vss
);

inv_x2_ins : inv_x2
port map (
i => b(1),
nq => inv_x2_sig,
vdd => vdd,
vss => vss
);

rtlcarry_0_2_ins : nao2o22_x1
port map (
i0 => inv_x2_sig,
i1 => a2_x2_sig,
i2 => not_rtlcarry_0_1,
i3 => not_a(1),
nq => rtlcarry_0_2,
vdd => vdd,
vss => vss
);

result_0_ins : xr2_x1
port map (
i0 => b(0),
i1 => a(0),
q => result(0),
vdd => vdd,
vss => vss
);

xr2_x1_ins : xr2_x1
port map (
i0 => a(1),
i1 => b(1),
q => xr2_x1_sig,
vdd => vdd,
vss => vss
);

result_1_ins : xr2_x1
port map (
i0 => xr2_x1_sig,
i1 => mbk_buf_rtlcarry_0_1,
q => result(1),
vdd => vdd,
vss => vss
);

xr2_x1_2_ins : xr2_x1
port map (
i0 => b(2),
i1 => a(2),
q => xr2_x1_2_sig,
vdd => vdd,
vss => vss
);

result_2_ins : xr2_x1
port map (
i0 => mbk_buf_rtlcarry_0_2,
i1 => xr2_x1_2_sig,
q => result(2),
vdd => vdd,
vss => vss
);

xr2_x1_3_ins : xr2_x1
port map (
i0 => a(3),
i1 => b(3),
q => xr2_x1_3_sig,
vdd => vdd,
vss => vss
);

a2_x2_2_ins : a2_x2
port map (
i0 => not_b(2),
i1 => not_rtlcarry_0_2,
q => a2_x2_2_sig,
vdd => vdd,
vss => vss
);

inv_x2_2_ins : inv_x2
port map (
i => a(2),
nq => inv_x2_2_sig,
vdd => vdd,
vss => vss
);

nao2o22_x1_ins : nao2o22_x1
port map (
i0 => inv_x2_2_sig,
i1 => a2_x2_2_sig,
i2 => not_rtlcarry_0_2,
i3 => not_b(2),
nq => nao2o22_x1_sig,
vdd => vdd,
vss => vss
);

result_3_ins : xr2_x1
port map (
i0 => nao2o22_x1_sig,
i1 => xr2_x1_3_sig,
q => result(3),
vdd => vdd,
vss => vss
);

mbk_buf_rtlcarry_0_1 : buf_x2
port map (
i => rtlcarry_0_1,
q => mbk_buf_rtlcarry_0_1,
vdd => vdd,
vss => vss
);

mbk_buf_rtlcarry_0_2 : buf_x2
port map (
i => rtlcarry_0_2,
q => mbk_buf_rtlcarry_0_2,
vdd => vdd,
vss => vss
);


end structural;



The list of cells found in Alliance library: For now it looks like that we just need to find out
a method to import the cells due to use Alliance logic synhesiser with Electric,
am I right?

a2_x2
a2_x4
a3_x2
a3_x4
a4_x2
a4_x4
an12_x1
an12_x4
ao22_x2
ao22_x4
ao2o22_x2
ao2o22_x4
buf_x2
buf_x4
buf_x8
fulladder_x2
fulladder_x4
halfadder_x2
halfadder_x4
inv_x1
inv_x2
inv_x4
inv_x8
mx2_x2
mx2_x4
mx3_x2
mx3_x4
na2_x1
na2_x4
na3_x1
na3_x4
na4_x1
na4_x4
nao22_x1
nao22_x4
nao2o22_x1
nao2o22_x4
nmx2_x1
nmx2_x4
nmx3_x1
nmx3_x4
no2_x1
no2_x4
no3_x1
no3_x4
no4_x1
no4_x4
noa22_x1
noa22_x4
noa2a22_x1
noa2a22_x4
noa2a2a23_x1
noa2a2a23_x4
noa2a2a2a24_x1
noa2a2a2a24_x4
noa2ao222_x1
noa2ao222_x4
noa3ao322_x1
noa3ao322_x4
nts_x1
nts_x2
nxr2_x1
nxr2_x4
o2_x2
o2_x4
o3_x2
o3_x4
o4_x2
o4_x4
oa22_x2
oa22_x4
oa2a22_x2
oa2a22_x4
oa2a2a23_x2
oa2a2a23_x4
oa2a2a2a24_x2
oa2a2a2a24_x4
oa2ao222_x2
oa2ao222_x4
oa3ao322_x2
oa3ao322_x4
on12_x1
on12_x4
one_x0
powmid_x0
powmid_x0
rowend_x0
rowend_x0
sff1_x4
sff2_x4
sff3_x4
tie_x0
tie_x0
ts_x4
ts_x8
xr2_x1
xr2_x4
zero_x0
Posted: December 13, 2010 09:13 by Dmitry Nadezhin
Ok. I adjusted Electric VHDL parser so that it can read this ".vst" format.
This is not in Electric-9.00, you need to checkout SVN version from java.net and to build it.

This program translated Alliance technology techno-035.rds to Electric technology. The conversion is incomplete. No DRC rules, pins and contacts are incorrect, etc.

Here is how to view the result.
  1. Update Electric SVN; build it; start it.
  2. Update electric-alliance~svn ;
  3. Select in Electric File|Preferences...|Technology|Added Technologies|Add".
  4. Choose tech file electric-alliance~svn/home/cyberflex/alliance/synth~example/lib-info/techno-035.xml".
  5. Open library electric-alliance~svn/home/cyberflex/alliance/synth~example/adder4/adder4-techno-035.jelib
  6. The TOP_LEVEL_UNNAMED{lay} contains Alliance and Electric results side-by-side.
  7. You can rebuild Electric result from adder4_vst{vhdl} .
Replies: 3 - Last Post: December 13, 2010 09:13
by: Dmitry Nadezhin
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